Using sequence to capture protocol violations

SystemVerilog
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2

In reply to yakirmishli:

I want to use sequence block to describe the expected behavior instead of using the support signal prev_e1_num. Any idea how to write it?

What’s wrong in using support logic, as long as your assertion is correct?

I want to write a sequence that describes two consecutive valid with e1_num incremented by 1.


logic				valid;
logic [common::log2(N)-1:0]	e1_num;
sequence q_really_consecutive; 
 valid[*2] ##0 e1_num==$past(e1_num -1'b1);
endsequence

sequence q_sparcely_consecutive; 
  logic [common::log2(N)-1:0]	v_e1;
  (valid, v_e1==e1_num) ##1 valid[->1] ##0 e1_num==v_e1 -1'b1);
endsequence

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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