Topic	Replies	Views	Activity
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	4	255	March 27, 2025
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	329	December 29, 2023
Can a register model be connected to 2 different adapters/agents ? One agent for write and another for read? UVM UVM , RAL-register-UVM	7	6774	July 26, 2023
Post_predict callback getting call twice in case reg sequence UVM SystemVerilog , UVM , RAL-register-UVM , uvm-ral	1	1039	September 27, 2021
UVM register Byte Enable UVM UVM , RAL-register-UVM , uvm-register-model-ofr-multiple-byte-register-in-soc , Number_Bytes	1	1986	December 1, 2020
Is using UVM register layer worth the effort for small projects? UVM UVM , RAL-register-UVM , uvm-ral , Why-using-RAL	5	1510	January 6, 2019
Why the call back post_predict is not call if you try to predict a register field with UVM_PREDICT_DIRECT? UVM UVM , UVM-callback , RAL-register-UVM	5	5679	November 27, 2015
Runtime addition/deletion of Register in RAL Model UVM UVM , RAL , RAL-register-UVM	1	1474	February 25, 2015
Coverage for Register Assistant Blocks UVM UVM , Cookbook-Registers , RAL-register-UVM	1	2602	June 3, 2014
Testing Read only Registers UVM UVM , RAL-register-UVM	3	7944	April 26, 2014

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