SV Assertion/Checker for stable input before the posedge of clock

SystemVerilog
, ,
1

There is a clock called clk.
There is an input signal called in1.
in1 has to be stable for at least 2 ns before the posedge of clk.
i.e. in1 cannot change within 2 ns before the posedge of clk.
How do I write an assertion/checker for this?
Please let me know.
Thanks!

2

If the tool supports the $setup, then you could use that.

// $setup ( data_event , reference_event , timing_check_limit [ , [ notifier ] ] ) ;
   // $setup( data, posedge clk, 10, notifier ) ;
   specify
      // Define timing check specparam values
   	  // Specify timing check variable must be a port.
      specparam tSU = 2, tHD = 1, tPW = 25, tWPC = 10, tREC = 5;
     $setup(in1, posedge clk, tSU); 
   endspecify

With assertions, you could do what I have below; basically create an event 2ns prior to @(posedge clk), and check that the signal has the same value @event and @(posedge clk)

module setup1(input bit clk, in1); 
	event e; 
	parameter PERIOD=10ns; 
	/*There is a clock called clk. 
There is an input signal called in1. 
in1 has to be stable for at least 2 ns before the posedge of clk.
i.e. in1 cannot change within 2 ns before the posedge of clk. 
How do I write an assertion/checker for this? */ 
  
   ap_setup0: assert property(@e !in1 |-> @(posedge clk)  !in1 );
   ap_setup1: assert property(@e in1 |-> @(posedge clk) in1 );
   always @(posedge clk) begin 
   	# (PERIOD -2ns); 
   	-> e; 
   end 
endmodule : setup1   

module top;
	bit clk, in1; 
	event e; 
	parameter PERIOD=10ns;  
	setup1 setup1_ins(.*); 
   initial forever #(PERIOD/2) clk=!clk; 
  
   
   initial begin 
     repeat(200) begin 
       @(posedge clk);   
       if (!randomize(in1)) $error(); 
     end 
   end 
endmodule : top
3

In reply to ben@SystemVerilog.us:

If you use the $setup, the variable ​in1 must be logic 4-state than 2 state.
Following code works OK.

module setup1(input logic clk, in1); 
	event e; 
	parameter PERIOD=10ns; 
	/*There is a clock called clk. 
There is an input signal called in1. 
in1 has to be stable for at least 2 ns before the posedge of clk.
i.e. in1 cannot change within 2 ns before the posedge of clk. 
How do I write an assertion/checker for this? */ 
  
   ap_setup0: assert property(@e !in1 |-> @(posedge clk)  !in1 );
   ap_setup1: assert property(@e in1 |-> @(posedge clk) in1 );
   // $setup ( data_event , reference_event , timing_check_limit [ , [ notifier ] ] ) ;
   // $setup( data, posedge clk, 10, notifier ) ;
   specify
      // Define timing check specparam values
   	  // Specify timing check variable must be a port.
      specparam tSU = 3, tHD = 1, tPW = 25, tWPC = 10, tREC = 5;
     $setup(in1, posedge clk, tSU);   // <------------------------------------
   endspecify
   
   always @(posedge clk) begin 
   	# (PERIOD -2ns); 
   	-> e; 
   end 
endmodule : setup1   

module top;
	logic clk=0, in1, in2; 
	event e; 
	parameter PERIOD=10ns;  
	setup1 setup1_ins(.*); 
   initial forever #(PERIOD/2) clk=!clk; 
  
   
   initial begin 
     repeat(200) begin 
       @(posedge clk);   
       if (!randomize(in2)) $error(); 
       #(PERIOD -2ns);
       in1 <= in2; 
     end 
   end 
endmodule : top

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
4

In reply to ben@SystemVerilog.us:

Thank You Ben!

5

In reply to new_to_uvm:

Hi Ben,

I have a query in the solution you gave.

" ap_setup0: assert property(@e !in1 |-> @(posedge clk) !in1 ); "

Consider consequent:
Suppose “in1” changes 0.1ns to 0.5ns before the posedge clk (considering timescale 1ns/1ns), it can’t be sampled; as the values sampled are not at the posedge clk, instead just before posedge clk. So, in this case setup violation occurs but i think this assertion can’t detect that. Is this correct?

Regards,
Dilip

6

In reply to Dilip Bagadi:

You are correct in that assertions uses events for the checks, and if in1 changes sometime before the @(posedge clk) the assertion will succeed, instead of failing. Actually, assertions are not intended for timing checks. In the audio field, undersampling is called “aliasing” Aliasing - Wikipedia
The best solution is to use the SystemVerilog timing checks that are defined in the language.

The following timing checks are discussed in this subclause:
$setup $hold $setuphold
$recovery $removal $recrem
These checks accept two signals, the reference event and the data event, and define a time window with
respect to one signal while checking the time of transition of the other signal with respect to the window. In general, they all perform the following steps:
a) Define a time window with respect to the reference signal using the specified limit or limits.
b) Check the time of transition of the data signal with respect to the time window.
c) Report a timing violation if the data signal transitions within the time window.

Ben Cohen

7

In reply to ben@SystemVerilog.us:

Thanks Ben…!!!