In reply to ben@SystemVerilog.us:
If you use the $setup, the variable in1 must be logic 4-state than 2 state.
Following code works OK.
module setup1(input logic clk, in1);
event e;
parameter PERIOD=10ns;
/*There is a clock called clk.
There is an input signal called in1.
in1 has to be stable for at least 2 ns before the posedge of clk.
i.e. in1 cannot change within 2 ns before the posedge of clk.
How do I write an assertion/checker for this? */
ap_setup0: assert property(@e !in1 |-> @(posedge clk) !in1 );
ap_setup1: assert property(@e in1 |-> @(posedge clk) in1 );
// $setup ( data_event , reference_event , timing_check_limit [ , [ notifier ] ] ) ;
// $setup( data, posedge clk, 10, notifier ) ;
specify
// Define timing check specparam values
// Specify timing check variable must be a port.
specparam tSU = 3, tHD = 1, tPW = 25, tWPC = 10, tREC = 5;
$setup(in1, posedge clk, tSU); // <------------------------------------
endspecify
always @(posedge clk) begin
# (PERIOD -2ns);
-> e;
end
endmodule : setup1
module top;
logic clk=0, in1, in2;
event e;
parameter PERIOD=10ns;
setup1 setup1_ins(.*);
initial forever #(PERIOD/2) clk=!clk;
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(in2)) $error();
#(PERIOD -2ns);
in1 <= in2;
end
end
endmodule : top
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115