In reply to new_to_uvm:
Hi Ben,
I have a query in the solution you gave.
" ap_setup0: assert property(@e !in1 |-> @(posedge clk) !in1 ); "
Consider consequent:
Suppose “in1” changes 0.1ns to 0.5ns before the posedge clk (considering timescale 1ns/1ns), it can’t be sampled; as the values sampled are not at the posedge clk, instead just before posedge clk. So, in this case setup violation occurs but i think this assertion can’t detect that. Is this correct?
Regards,
Dilip