SV and vhdl Dut connection

UVM
, ,
1

Hi,
In uvm environment I want connect .sv(TB) and design in vhdl. How to represent record under record in systemverilog struct?


 type abc_t is
  record
  valid  :std_logic
  data : std_logic_vector(7 downto 0);
  end record;
  type a is array (5 downto 0) of abc_t;
  type b is array (3 downto 0) of a;
  
  type bcd_t is
   record
    efg : b
   end record;

How to represent above code in system verilog?

2

In reply to poonamnlwd:

Please use code tags making your code easier to read. I have added them for you.

There is no standard that defines the interaction between VHDL and SystemVerilog, although most simulation tools provide methods to connect the two. You will need to refer to your tool documentation or contact your tool vendor for additional assistance.

3

In reply to poonamnlwd:

Hi,
In uvm environment I want connect .sv(TB) and design in vhdl. How to represent record under record in systemverilog struct?


type abc_t is
record
valid  :std_logic
data : std_logic_vector(7 downto 0);
end record;
type a is array (5 downto 0) of abc_t;
type b is array (3 downto 0) of a;
type bcd_t is
record
efg : b
end record;

How to represent above code in system verilog?

You could do it like this:

package my_sv_types;
typedef struct packed {
     logic val;
     logic [7:0] dat;
     } abc_sv_t;

typedef abc_sv_t [5:0] a;   
typedef a [3:0] b;   

typedef struct packed {
     b efg;
    } bcd_sv_t;

endpackage
4

In reply to chr_sue:


typedef struct {
  bit val;
  bit [7:0] data;
}abc_t;

typedef abc_t a[6];
typedef a b[4];

typedef struct {
  b efg;
}bcd_sv_t

type a is array (5 downto 0) of abc_t;
5 downto 0 is considered as a width or depth?

5

In reply to poonamnlwd:

This does not matter. See the code example below.

package my_sv_types;
typedef struct packed {
     logic val;
     logic [7:0] dat;
     } abc_sv_t;

typedef abc_sv_t [6] a;   
typedef a [4] b;   

typedef struct packed {
     b efg;
    } bcd_sv_t;

endpackage


module tb;
  import my_sv_types::*;
  logic clk;
  a     sig1 = '{'{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}};
  b     sig2;
  abc_sv_t [5:0] sig3;
  bcd_sv_t [3:0] sig4;

  abc_sv_t [0:5] sig5;
  bcd_sv_t [0:3] sig6;

  initial begin
    sig3 = sig1;
    #10;
    sig5 = sig1;
    #10;
  end
endmodule
6

In reply to chr_sue:

Thank you for an example