SV and vhdl Dut connection

UVM
, ,
5

In reply to poonamnlwd:

This does not matter. See the code example below.

package my_sv_types;
typedef struct packed {
     logic val;
     logic [7:0] dat;
     } abc_sv_t;

typedef abc_sv_t [6] a;   
typedef a [4] b;   

typedef struct packed {
     b efg;
    } bcd_sv_t;

endpackage


module tb;
  import my_sv_types::*;
  logic clk;
  a     sig1 = '{'{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}, '{1'b0, 8'h55}};
  b     sig2;
  abc_sv_t [5:0] sig3;
  bcd_sv_t [3:0] sig4;

  abc_sv_t [0:5] sig5;
  bcd_sv_t [0:3] sig6;

  initial begin
    sig3 = sig1;
    #10;
    sig5 = sig1;
    #10;
  end
endmodule