SV and vhdl Dut connection

UVM
, ,
3

In reply to poonamnlwd:

Hi,
In uvm environment I want connect .sv(TB) and design in vhdl. How to represent record under record in systemverilog struct?


type abc_t is
record
valid  :std_logic
data : std_logic_vector(7 downto 0);
end record;
type a is array (5 downto 0) of abc_t;
type b is array (3 downto 0) of a;
type bcd_t is
record
efg : b
end record;

How to represent above code in system verilog?

You could do it like this:

package my_sv_types;
typedef struct packed {
     logic val;
     logic [7:0] dat;
     } abc_sv_t;

typedef abc_sv_t [5:0] a;   
typedef a [3:0] b;   

typedef struct packed {
     b efg;
    } bcd_sv_t;

endpackage