Reporting of assertion failures as uvm_errors

UVM
, ,
1

Hi

I have coded the assertions inside TOP TB (between module and endmodule)

i am using $error for specifying the failures when the assertions fails but if i want the assertion error to be reported as UVM_ERROR

what will be the best way to achieve the above.

Currently i am setting a flag in the else part of the assertion and using that flag in the test to report it as a UVM_ERROR,

but in my usage the uvm_error won’t be reporting the multiple failures of the assertions.

Thanks & Regards
Siva

2

The code below demonstrates the concepts, as explained in my SVA Handbook, 3rd Edition.

import uvm_pkg::*;  `include "uvm_macros.svh"
module uvm_sva_ex;   // File c/uvm_sva_ex.sv
    bit clk, a, b, c, req, ack; 
    parameter CLK_HPERIOD = 10;
    string tID="UART ";
    initial begin : clk_gen forever #CLK_HPERIOD clk <= !clk; end : clk_gen
    default clocking def_cb @ (posedge clk);  endclocking : def_cb
    ap_LOW: assert property(a) else
        `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_LOW); // Line 9
    ap_MEDIUM: assert property(a) else
        `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_MEDIUM); // Line 11
    ap_HIGH: assert property(a) else
        `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_HIGH);   // Line 13
    ap_FULL: assert property(a) else
        `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_FULL);   // Line 15
    ap_test2: assert property(a) else
        `uvm_error(tID,$sformatf("%m : error in a %b", a));       // Line 17
    ap_handshake0 : assert property ($rose(req) |=> ##[0:4] ack) else
        $error(tID, $sformatf("%m req = %0h, ack=%0h",                
                       $sampled(req), $sampled (ack)));   // Line 20
    ap_handshake : assert property ($rose(req) |=> ##[0:4] ack) else
        `uvm_error(tID, $sformatf("%m req = %0h, ack=%0h",            
              $sampled(req), $sampled (ack)));   // Line 23   
    //… 
endmodule : uvm_sva_ex

Simulation produced the following results:
compilation_command uvm_sva_ex.sv
simulation_command +UVM_VERBOSITY=UVM_HIGH uvm_sva_ex
…
run 400ns
…
# UVM_INFO uvm_sva_ex.sv(13) @ 10: reporter [UART ] uvm_sva_ex.ap_HIGH : error in a 0
# UVM_ERROR uvm_sva_ex.sv(17) @ 10: reporter [UART ] uvm_sva_ex.ap_test2 : error in a 0
# UVM_INFO uvm_sva_ex.sv(11) @ 10: reporter [UART ] uvm_sva_ex.ap_MEDIUM : error in a 0
# UVM_INFO uvm_sva_ex.sv(9) @ 10: reporter [UART ] uvm_sva_ex.ap_LOW : error in a 0
# UVM_INFO uvm_sva_ex.sv(13) @ 30: reporter [UART ] uvm_sva_ex.ap_HIGH : error in a 0
# UVM_ERROR uvm_sva_ex.sv(17) @ 30: reporter [UART ] uvm_sva_ex.ap_test2 : error in a 0
# UVM_INFO uvm_sva_ex.sv(11) @ 30: reporter [UART ] uvm_sva_ex.ap_MEDIUM : error in a 0
# UVM_INFO uvm_sva_ex.sv(9) @ 30: reporter [UART ] uvm_sva_ex.ap_LOW : error in a 0
# UVM_INFO uvm_sva_ex.sv(13) @ 50: reporter [UART ] uvm_sva_ex.ap_HIGH : error in a 1
# UVM_ERROR uvm_sva_ex.sv(17) @ 50: reporter [UART ] uvm_sva_ex.ap_test2 : error in a 1
# UVM_INFO uvm_sva_ex.sv(11) @ 50: reporter [UART ] uvm_sva_ex.ap_MEDIUM : error in a 1
# UVM_INFO uvm_sva_ex.sv(9) @ 50: reporter [UART ] uvm_sva_ex.ap_LOW : error in a 1
# ** Error: UART uvm_sva_ex.ap_handshake0 req = 0, ack=0
# Time: 170 ns Started: 70 ns Scope: uvm_sva_ex.ap_handshake0 File: uvm_sva_ex.sv Line: 20 Expr: ack
# UVM_ERROR uvm_sva_ex.sv(23) @ 170: reporter [UART ] uvm_sva_ex.ap_handshake req = 0, ack=0

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Thanks Ben i have implemented this in my code its working fine.

4

In reply to ben@SystemVerilog.us:

Ben,

What if rtl design has $error and I cannot edit that file? Is there a way to overwrite $error with `uvm_error?

5

In reply to tomrohit:

In reply to ben@SystemVerilog.us:
Ben,
What if rtl design has $error and I cannot edit that file? Is there a way to overwrite $error with `uvm_error?

Apologies, the $error should have been a uvm_error as shown in the assertion example. Yes, you can substitute $error with uvm_error anywhere.

ap_handshake : assert property ($rose(req) |=> ##[0:4] ack) else
        `uvm_error(tID, $sformatf("%m req = %0h, ack=%0h",            
              $sampled(req), $sampled (ack)));   // Line 23

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

6

In reply to ben@SystemVerilog.us:

I cannot edit the design file to replace $error with `uvm_error. Is there any way to do overloading or something else?
I want to turn off some assertions on failure, was thinking of using uvm demoter but cannot use on $error.

7

In reply to tomrohit:
You need to find the person who is able to edit the file and get them to change it.

There are tool specific ways of disabling assertions if the assertion has a label. But that will never give you the full flexibility that `uvm_error provides.

8

In reply to tomrohit:

If you use Questa, here is a simple way to do this. http://www.veriflabs.com/assertion-failures-via-uvm-automated/

Good Luck
Srini
www.verifworks.com