In reply to tomrohit:
In reply to ben@SystemVerilog.us:
Ben,
What if rtl design has $error and I cannot edit that file? Is there a way to overwrite $error with `uvm_error?
Apologies, the $error should have been a uvm_error as shown in the assertion example. Yes, you can substitute $error with uvm_error anywhere.
ap_handshake : assert property ($rose(req) |=> ##[0:4] ack) else
`uvm_error(tID, $sformatf("%m req = %0h, ack=%0h",
$sampled(req), $sampled (ack))); // Line 23
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115