Elene
November 9, 2022, 1:44pm
1
If pkg is imported inside module, the code inside `ifdef is not parsed during compilation.
when pkg is defined outside the module everything works fine. Do you know what can be reason for that?
package pkg_with_defines;
`define DATA
endpackage
module tb_top;
import pkg_with_defines::*;
´ifdef DATA
logic bit data;
endif
...
endmodule
cgales
November 9, 2022, 2:11pm
2
In reply to EleneSajaia :
The `define is a pre-processor macro and is not part of the package. This is why it can’t be imported.
You need to specify DATA when compiling tb_top if you want it to be utilized.
Elene
November 9, 2022, 2:49pm
3
In reply to cgales :
`define DATA is part of pkg but when it is imported outside module, my test is passing. How is that possible?
package pkg_with_defines;
`define DATA
endpackage
inside tb_top.sv
import pkg_with_defines::*;
module tb_top;
´ifdef DATA
logic bit data;
endif
...
endmodule
cgales
November 9, 2022, 3:07pm
4
In reply to EleneSajaia :
You are likely compiling both files at the same time. In this case, the `define will carry over from the package file to the tb_top.sv.
In reply to EleneSajaia :
FYI, this example helps show that compiler directives get pre-processed as a distinct step before SystemVerilog compilation.
package pkg_A;
`define DATA "hello"
endpackage
package pkg_B;
`define DATA "world"
endpackage
module tb_top;
import pkg_A::*;
initial $display(`DATA);
endmodule
Elene
November 10, 2022, 7:12pm
7
In reply to dave_59 :
Thanks Dave. It makes sense now. Decided to not to use `defines.