Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it?

SystemVerilog
, , ,
3

In reply to cgales:

`define DATA is part of pkg but when it is imported outside module, my test is passing. How is that possible?



package pkg_with_defines;
 
`define DATA
 
endpackage

inside tb_top.sv


import pkg_with_defines::*;
module tb_top;
 
´ifdef DATA
 logic bit data;
 endif
...
endmodule