Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it?

SystemVerilog
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6

In reply to EleneSajaia:

FYI, this example helps show that compiler directives get pre-processed as a distinct step before SystemVerilog compilation.

package pkg_A;
 
`define DATA "hello"
 
endpackage

package pkg_B;
 
`define DATA "world"
 
endpackage


module tb_top;
  
import pkg_A::*;
  
  initial $display(`DATA);
 

endmodule