I want to write an assertion where genclock must rise in the setup or hold time window(say 2ns each) of refclock. Is there a in built timing check for this?

SystemVerilog
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In reply to soh2415:

Hey, so generally speaking SVA are not intended to be used to check timing, I’d recommend using the Systemverilog timing system task like $setup $hold $width and $period.

My suggestion is to create a module called timing check and encapsulate those tasks into a specify endspecify. All those tasks, mainly setup and hold (which i believe are the ones you should be using) provide and output called notifier. You can use this bit to check if the timing constraint has been violated.