I want to write an assertion where genclock must rise in the setup or hold time window(say 2ns each) of refclock. Is there a in built timing check for this?

SystemVerilog
, ,
4

In reply to soh2415:
Here is an example that you can use as a guideline:


 module top2(output logic clk, d);
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    timeunit 1ns;  timeprecision 100ps;    
    logic a, d1;
    bit[1:0] delay;
    realtime duration= 2.0ns; 
    initial begin 
        clk=0; 
        forever #5 clk = !clk;
    end
    always @(posedge clk) begin
        if (!randomize(a, delay) with {
           delay  dist {2'b01 := 1, 2'b11 := 1};
          }) `uvm_error("MYERR", "This is a randomize error");    
          #delay d<=a; 
    end

    property hold_chk;
        realtime clock_sample;
         @(posedge clk)
        (1,clock_sample = $realtime)##0 (1,$display("clock_sample=%0t",clock_sample)) |-> 
        @(d)((1,$display("data_sample=%0t,difference=%0t",$realtime,$realtime-clock_sample))##0
        ($realtime - clock_sample) >= duration);
    endproperty : hold_chk
        
    HOLD_CHK : assert property (hold_chk)
        // $display("****ASSERTION_PASSED**** clock");
        else	
        	$display ("%0t ERROR Hold****",$realtime);
   
            property setup_chk;
                realtime clock_sample;
                 @(d)
                (1,clock_sample = $realtime)##0 (1,$display("d_sample=%0t",clock_sample)) |-> 
                @(posedge clk)((1,$display("clk_sample=%0t,difference=%0t",$realtime,$realtime-clock_sample))##0
                ($realtime - clock_sample) >= duration);
            endproperty : setup_chk
                
            SETUP_CHK : assert property (setup_chk)
                // $display("****ASSERTION_PASSED**** clock");
                else	
                    $display ("%0t ERROR setup****",$realtime);

    setup_time_check setup_time_check1(clk, d); 

    initial #2000 $finish; 
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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