I want to override base sequence written inside my base test with virtual sequence from command line argument using factory override, I have read a paper from Sunburst about factory but it is being explained from code using set_inst_override_by_type method which will not be done from command line, but I want to override from command line. So can you please guide me to do this?
In reply to Mahammadshahid Shaikh:
It’s recommended that you create a new test which does the override instead of using a command line argument. The reason for this is that when running regressions, it is easier to add a new test to your list of tests than it is to try and manipulate command line arguments. Also, when analyzing test results, it is easier to correlate results by test name than by trying to determine which command line arguments were used.
I have considered that scenario of new test which override but my current requirement is to have only base test with base sequence and I need to run using python script and for required testcase, selected virtual sequence is to be given from script directly. So, that’s why I need to understand, how to override the base sequence with virtual sequence using command line argument.
In reply to Mahammadshahid Shaikh:
I am not sure understand what your question is. Do you already know how to register classes with the UVM factory and then call create() to construct the base sequence?
Then there is the UVM command line processor to select the type override: +uvm_set_type_override=< req_type >,< override_type >. Are you asking about how to use that switch?
Yes, I was asking about the same, I am not understanding how to use this command line processor switch.
In reply to Mahammadshahid Shaikh:
Here is a simple example. Run this with the run-time command line +uvm_set_type_override=base,derived
import uvm_pkg::*;
`include "uvm_macros.svh"
class base extends uvm_object;
`uvm_object_utils(base)
function new(string name="base"); super.new(name); endfunction
virtual function void print;
`uvm_info("print","from base",UVM_LOW)
endfunction
endclass
class derived extends base;
`uvm_object_utils(derived)
function new(string name="derived"); super.new(name); endfunction
virtual function void print;
`uvm_info("print","from derived",UVM_LOW)
endfunction
endclass
class test extends uvm_test;
`uvm_component_utils(test)
function new(string name="derived",uvm_component parent=null); super.new(name,parent); endfunction
base b;
function void build_phase(uvm_phase phase);
b = base::type_id::create("b");
b.print();
endfunction
endclass
module top;
initial run_test("test");
endmodule
Thanks Dave, I have understood!
In reply to dave_59:
Hi Dave ,
Out of curiosity :
(1) Are the run-time arguments applicable for all UVM versions ( UVM1.1d , UVM1.2 ) ?
(2) Also how are the overrides actually registered in the factory ?
Eg: uvm_root looks for +UVM_TESTNAME in it’s task run_test , so who looks for these switches : +uvm_set_type_override and +uvm_set_inst_override ?
Are they registered during a specific phase ? OR even prior to phasing ?
In reply to ABD_91:
The UVM command line processor has been there since before UVM-1.1d.
Factory registration happens as part of static variable initialization at time 0 before any phases begin. (Before any initial/always processes start)
See this link for more details. It was written for the OVM, but everything still applies for the UVM.
In reply to dave_59:
Thanks Dave ,
I went through the UVM BCL for the same . Turns out : build_phase() of uvm_root looks for the command-line argument : +uvm_set_type_override/+UVM_SET_TYPE_OVERRIDE and +uvm_set_inst_override/+UVM_SET_INST_OVERRIDE via uvm_cmdline_processor.
Similarly run-time switch +UVM_MAX_QUIT_COUNT is processed in build_phase() of uvm_root
However I observe that phasing starts after creating the Test component ,
// Within uvm_root::run_test
.............
$cast(uvm_test_top, factory.create_component_by_name(test_name,
"", "uvm_test_top", null));
// At this point the Test component passed via +UVM_TESTNAME=.. has been created already
// Phasing starts later
fork begin
// spawn the phase runner task
phase_runner_proc = process::self();
uvm_phase::m_run_phases();
end
join_none
#0; // let the phase runner start
..............
As the run-time switches are checked in build_phase of uvm_root i.e after phasing starts .
This essentially means that overrides specified via run-time switches are registered in factory after Test component is created.
(1) So this means that via +uvm_set_type_override and +uvm_set_inst_override , user can’t override the +UVM_TESTNAME=Test component right ?
(2) Who calls the build_phase() of uvm_root ? Is it called before build_phase() of Test component ?
In reply to ABD_91:
In UVM, the components are static, and their hierarchy is created during the build phase. Any component override must happen during the build phase. On the other hand, UVM object, sequence override can happen at any time as long as they have not been created in the build phase.
The test is starting point it’s picked up the following line in uvm_root.svh file
// Retrieve the test names provided on the command line. Command line
// overrides the argument.
test_name_count = clp.get_arg_values(“+UVM_TESTNAME=”, test_names);
//
What’s the point of an overriding test case as its starting point/entry point of execution?
In reply to kddholak:
In UVM, the components are static
Quasi-static to be precise.
What’s the point of an overriding test case as its starting point/entry point of execution?
Here is an application :
There is no run-time argument via +UVM_TESTNAME and a base_test is given as string argument to run_test in top_tb
Then using the run-time switches I would override the base test
In reply to ABD_91:
+UVM_TESTNAME already overrides the testname argument supplied to run_test. So if you are going to override the test, use +UVM_TESTNAME=, not +uvm_set_type_override=
In reply to dave_59:
+UVM_TESTNAME already overrides the testname argument supplied to run_test.
Yes , I am aware of this.
I was curious if instead of +UVM_TESTNAME=TEST , what if user specifies +uvm_set_type_override=base_test,TEST ( as both are run-time arguments ).
I haven’t tested it out but the BCL tells me that the overrides won’t take effect as the Test component is created prior to checking +uvm_set_type_override= and registering the override in factory.
As the switch +uvm_set_type_override= is processed in build_phase() of uvm_root , I was curious how is build_phase() of uvm_root called ?
Is it called via : uvm_phase::m_run_phases()
In reply to ABD_91:
uvm_pkg::run_test() calls uvm_root::run_test. That reads the command line and start execution of the phases.