How to override base sequence with virtual sequence from command line using factory?

In reply to dave_59:

Thanks Dave ,
I went through the UVM BCL for the same . Turns out : build_phase() of uvm_root looks for the command-line argument : +uvm_set_type_override/+UVM_SET_TYPE_OVERRIDE and +uvm_set_inst_override/+UVM_SET_INST_OVERRIDE via uvm_cmdline_processor.

Similarly run-time switch +UVM_MAX_QUIT_COUNT is processed in build_phase() of uvm_root

However I observe that phasing starts after creating the Test component ,


 // Within uvm_root::run_test 
 .............
 $cast(uvm_test_top, factory.create_component_by_name(test_name,
          "", "uvm_test_top", null));
 // At this point the Test component passed via +UVM_TESTNAME=.. has been created already
 
 // Phasing starts later
    fork begin
    // spawn the phase runner task
    phase_runner_proc = process::self();
    uvm_phase::m_run_phases();
  end
  join_none
  #0; // let the phase runner start

 ..............

As the run-time switches are checked in build_phase of uvm_root i.e after phasing starts .
This essentially means that overrides specified via run-time switches are registered in factory after Test component is created.

(1) So this means that via +uvm_set_type_override and +uvm_set_inst_override , user can’t override the +UVM_TESTNAME=Test component right ?

(2) Who calls the build_phase() of uvm_root ? Is it called before build_phase() of Test component ?