In reply to ABD_91:
In UVM, the components are static, and their hierarchy is created during the build phase. Any component override must happen during the build phase. On the other hand, UVM object, sequence override can happen at any time as long as they have not been created in the build phase.
The test is starting point it’s picked up the following line in uvm_root.svh file
// Retrieve the test names provided on the command line. Command line
// overrides the argument.
test_name_count = clp.get_arg_values(“+UVM_TESTNAME=”, test_names);
//
What’s the point of an overriding test case as its starting point/entry point of execution?