How to override base sequence with virtual sequence from command line using factory?

In reply to dave_59:

Hi Dave ,
Out of curiosity :

(1) Are the run-time arguments applicable for all UVM versions ( UVM1.1d , UVM1.2 ) ?

(2) Also how are the overrides actually registered in the factory ?
Eg: uvm_root looks for +UVM_TESTNAME in it’s task run_test , so who looks for these switches : +uvm_set_type_override and +uvm_set_inst_override ?
Are they registered during a specific phase ? OR even prior to phasing ?