How to override base sequence with virtual sequence from command line using factory?

In reply to kddholak:

In UVM, the components are static

Quasi-static to be precise.

What’s the point of an overriding test case as its starting point/entry point of execution?

Here is an application :
There is no run-time argument via +UVM_TESTNAME and a base_test is given as string argument to run_test in top_tb

Then using the run-time switches I would override the base test