How can two interface have the same clock and reset?

UVM
,
1

I have two interface:

interface pakmx_if_in ();
logic clk;
logic rst;
logic [7:0] data_in;
logic data_en;
logic packet_start;
logic packet_err;
logic busy;
endinterface

interface pakmx_if_out ();
logic ch_data_en;
logic ch_start;
logic [7:0] ch_data;
endinterface

I want that thw output interface (pakmx_if_out) will have the same clk and reset as pakmx_if_in.
How can I do it?

2

In reply to saritr:

You have 2 options:
(1) I presume clk and rst are inputs to both interfaces. Then pass them as arguments to both interfaces:

interface pakmx_if_in (input logic clk, input logic rst);
....
endinterface
interface pakmx_if_out (input logic clk, input logic rst);

endinterface

clk and reset will be generated in the toplevel module.

(2) You add both signals to the interface description like this:

interface pakmx_if_in ();
logic clk;
logic rst;
....
endinterface
interface pakmx_if_out ();
logic clk;
logic rst;
.....
endinterface
3

In reply to saritr:

All shared signals between interfaces should be made a ports of your interface.

interface pakmx_if_in (input logic clk, input logic rst);
logic [7:0] data_in;
logic data_en;
logic packet_start;
logic packet_err;
logic busy;
endinterface
interface pakmx_if_out (input logic clk, input logic rst);
 logic ch_data_en;
logic ch_start;
logic [7:0] ch_data;
endinterface

module top;

logic clk, rst;

pakmx_if_in   if_in(.*)
pakmx_if_out  if_out(.*);

...
endmodule

If one interface is the source of the clk or reset, then change the
input to
output accordingly.

4

In reply to chr_sue:

In reply to saritr:
You have 2 options:
(1) I presume clk and rst are inputs to both interfaces. Then pass them as arguments to both interfaces:

interface pakmx_if_in (input logic clk, input logic rst);
....
endinterface
interface pakmx_if_out (input logic clk, input logic rst);
endinterface

clk and reset will be generated in the toplevel module.
(2) You add both signals to the interface description like this:

interface pakmx_if_in ();
logic clk;
logic rst;
....
endinterface
interface pakmx_if_out ();
logic clk;
logic rst;
.....
endinterface

I want to use option 2.
I don’t understand how each of the ckl and rst “know” that it’s the same like the other interface. Where I have to connect them?

5

In reply to saritr:

You’ll have the instances of both interfaces in the toplevel module.
If you are generating clk and rst in this moule you have to connect them to the interface signals accordingly.

6

In reply to chr_sue:

In reply to saritr:
You’ll have the instances of both interfaces in the toplevel module.
If you are generating clk and rst in this moule you have to connect them to the interface signals accordingly.

Like this:
//Clock generation
initial vif_in.clk = 1’b1;
always #5ns vif_in.clk = ~vif_in.clk;
initial vif_out.clk = 1’b1;
always #5ns vif_out.clk = ~vif_out.clk;

//rst
initial begin
vif_in.rst = 1’b1;
@(posedge vif_in.clk);
vif_in.rst = 1’b0;
vif_out.rst = 1’b1;
@(posedge vif_out.clk);
vif_out.rst = 1’b0;

end

7

In reply to saritr:

Yes something like this. In your case rst is different for both interfaces.

8

In reply to chr_sue:

No, it’s the same.

9

In reply to saritr:

initial begin
vif_in.rst = 1’b1;
@(posedge vif_in.clk);
vif_in.rst = 1’b0;
vif_out.rst = 1’b1; // is this a typo?
@(posedge vif_out.clk);
vif_out.rst = 1’b0;

end

See my remark above, please.