In reply to chr_sue:
In reply to saritr:
You’ll have the instances of both interfaces in the toplevel module.
If you are generating clk and rst in this moule you have to connect them to the interface signals accordingly.
Like this:
//Clock generation
initial vif_in.clk = 1’b1;
always #5ns vif_in.clk = ~vif_in.clk;
initial vif_out.clk = 1’b1;
always #5ns vif_out.clk = ~vif_out.clk;
//rst
initial begin
vif_in.rst = 1’b1;
@(posedge vif_in.clk);
vif_in.rst = 1’b0;
vif_out.rst = 1’b1;
@(posedge vif_out.clk);
vif_out.rst = 1’b0;
end