In reply to chr_sue:
In reply to saritr:
You have 2 options:
(1) I presume clk and rst are inputs to both interfaces. Then pass them as arguments to both interfaces:
interface pakmx_if_in (input logic clk, input logic rst);
....
endinterface
interface pakmx_if_out (input logic clk, input logic rst);
endinterface
clk and reset will be generated in the toplevel module.
(2) You add both signals to the interface description like this:
interface pakmx_if_in ();
logic clk;
logic rst;
....
endinterface
interface pakmx_if_out ();
logic clk;
logic rst;
.....
endinterface
I want to use option 2.
I don’t understand how each of the ckl and rst “know” that it’s the same like the other interface. Where I have to connect them?