How can two interface have the same clock and reset?

In reply to saritr:

All shared signals between interfaces should be made a ports of your interface.

interface pakmx_if_in (input logic clk, input logic rst);
logic [7:0] data_in;
logic data_en;
logic packet_start;
logic packet_err;
logic busy;
endinterface
interface pakmx_if_out (input logic clk, input logic rst);
 logic ch_data_en;
logic ch_start;
logic [7:0] ch_data;
endinterface

module top;

logic clk, rst;

pakmx_if_in   if_in(.*)
pakmx_if_out  if_out(.*);

...
endmodule

If one interface is the source of the clk or reset, then change the
input
to
output
accordingly.