Hierarchical reference from package not allowed

[Ahmed_Kelany]

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Accessing hierarichal nets inside system verilog packages

In the paper "Abstract BFM", in Figure 1, the authors show the system Verilog package access hierarichal nets. package stimulus_pkg; class Stimgen; task run(); repeat(10) begin #5 testbench_Top.R = 1'b0; #5 testbench_Top.R = 1'b1; end endtask endclass endpackage As per my understanding, this is wrong. I checked in EdaPlayground and got the error that I expected. Is something I am missing?