Error while assigning an array in generate block

SystemVerilog
, , , , ,
1 
function void display(logic [5:0] llr_data);
   $display(" llr_data %0h",llr_data);
endfunction


property data_valid(temp);   
        //logic [5:0] llr_data;
        @(posedge vld)
        (vld, display(temp)) |-> (temp >= -'d32 and temp <= 'd32);  
endproperty


generate
  
    for(genvar j =0; j<32; j=j+1)
      begin
          temp[j] <= {6{data >> (j*6)}};
          //$display("Temp %0h i:%0d time%0t",temp[j],i,$time);
          assert property (data_valid(temp[j]));
        //j=j+1;
        end
      
endgenerate

above is my code in a module. I’m getting the following error.
temp[j] <= {6{data >> (j*6)}};
|
41091 xmvlog: E,EXPLPA (/_sva_cov.sv,133|14): expecting a left parenthesis (‘(’) [12.1.2][7.1(IEEE)].

The declaration of temp is logic [5:0] temp[0:TEMP_SIZE-1]; where SIZE = 32. Also if I use $display it shows me an error. The main purpose is to assert the property @posedge vld, to latch the data and Please help!

2

In reply to Nimisha Varadkar:
Per 1800 27.2 Overview
Generate constructs are used to either conditionally or multiply instantiate generate blocks into a model. Thus,

 
generate  for(genvar j =0; j<32; j=j+1)
         begin
          temp[j] <= {6{data >> (j*6)}}; //  <<---- This is NOT a block 
// Below is a block with the always
// Below is OK,  DO you need this? 
generate  for(genvar j =0; j<32; j=j+1)
         begin
            always  @(posedge vld) begin 
              temp[j] = {6{data >> (j*6)}};
             assert property (data_valid(temp[j])); 
            end 
           end
   endgenerate

// Is  your intention is to do the following? 
generate  for(genvar j =0; j<32; j=j+1)  begin    
             assert property (data_valid(temp[j])); 
           end
    
   endgenerate
    
   initial   
    for( int j =0; j<32; j=j+1)
         temp[j] <= {6{data >> (j*6)}};

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to Nimisha Varadkar:

Please use code tags making your code easier to read. I have added them for you.

You are attempting to put a procedural NBA statement inside a generate loop. The code inside a generate-for loop is at the module level unless you put an initial always block inside it. What you probably want to do is:

  for(genvar j =0; j<32; j=j+1)
      begin
          let temp = {6{data >> (j*6)}};
          assert property (data_valid(temp));
        end

Also, the expression
temp >= -'d32 and temp <= 'd32 will not work unless temp is a signed variable type.

4

In reply to ben@SystemVerilog.us:

My intention is to latch the data in temp only when vld is high, so I included it in the always_ff block.