Error while assigning an array in generate block

SystemVerilog
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2

In reply to Nimisha Varadkar:
Per 1800 27.2 Overview
Generate constructs are used to either conditionally or multiply instantiate generate blocks into a model. Thus,

 
generate  for(genvar j =0; j<32; j=j+1)
         begin
          temp[j] <= {6{data >> (j*6)}}; //  <<---- This is NOT a block 
// Below is a block with the always
// Below is OK,  DO you need this? 
generate  for(genvar j =0; j<32; j=j+1)
         begin
            always  @(posedge vld) begin 
              temp[j] = {6{data >> (j*6)}};
             assert property (data_valid(temp[j])); 
            end 
           end
   endgenerate

// Is  your intention is to do the following? 
generate  for(genvar j =0; j<32; j=j+1)  begin    
             assert property (data_valid(temp[j])); 
           end
    
   endgenerate
    
   initial   
    for( int j =0; j<32; j=j+1)
         temp[j] <= {6{data >> (j*6)}};

Ben Cohen
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