Error while assigning an array in generate block

SystemVerilog
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3

In reply to Nimisha Varadkar:

Please use code tags making your code easier to read. I have added them for you.

You are attempting to put a procedural NBA statement inside a generate loop. The code inside a generate-for loop is at the module level unless you put an initial always block inside it. What you probably want to do is:

  for(genvar j =0; j<32; j=j+1)
      begin
          let temp = {6{data >> (j*6)}};
          assert property (data_valid(temp));
        end

Also, the expression
temp >= -'d32 and temp <= 'd32 will not work unless temp is a signed variable type.