Dynamic delay assertion

SystemVerilog
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1

Hi,

I want to write an assertion like below pseudo code:

virtual interface user_if vif;
@(posedge clk)
output ##(vif.delay) input;

Now here, my delay is driven from the virtual sequence and keep changing during sim hence, dynamic delay.
What’s the easiest/simplest way to write this?

Thank you in advance.

1 Like
2

In reply to chandnidodiya:
Where are you applying the assertion?
If it’s in the interface then you can use my package at
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
From the package you need to apply


   sequence dynamic_delay(count);
        int v;
      (count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
    endsequence // dynamic_delay
// in your interface 
interface name; 
  import sva_delay_repeat_range_pkg::*;
  int delay=2; // can be reassigned as needed later on 
  property p; 
    int v; 
    (1, v=input1) ##0 dynamic_delay(delay) ##0 output1==v; 
  endproperty 
  ap_dyn_delay: assert property(@(posedge clk) p);

From your code, it seems that you want to do the assertion from the class.
SVA does not support uses in classes, but you have 2 options:

  1. Copy the class variables into the virtual interface that has the SVA as shown above.
    I addressed that in my paper SVA-in-a-UVM-Class-based-Environment
  2. Create a task that at every clock edge initiates a forked task that computes this assertion. Read my paper Understanding the SVA Engine (link to the paper is in my signature).

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/

3

In reply to ben@SystemVerilog.us:

My assertion is in test bench top module.

4

In reply to chandnidodiya:


module top;
  import sva_delay_repeat_range_pkg::*;
  int delay=2; // can be reassigned as needed later on 
  input_type input1, output1;  // can be int, bit vector, ....
  property p; // give it a meaningful name 
    input_type v; 
    (1, v=input1) ##0 dynamic_delay(delay) ##0 output1==v; 
  endproperty 
  ap_dyn_delay: assert property(@(posedge clk) p);