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Now here, my delay is driven from the virtual sequence and keep changing during sim hence, dynamic delay.
What’s the easiest/simplest way to write this?
sequence dynamic_delay(count);
int v;
(count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
endsequence // dynamic_delay
// in your interface
interface name;
import sva_delay_repeat_range_pkg::*;
int delay=2; // can be reassigned as needed later on
property p;
int v;
(1, v=input1) ##0 dynamic_delay(delay) ##0 output1==v;
endproperty
ap_dyn_delay: assert property(@(posedge clk) p);
From your code, it seems that you want to do the assertion from the class.
SVA does not support uses in classes, but you have 2 options:
Copy the class variables into the virtual interface that has the SVA as shown above.
I addressed that in my paper SVA-in-a-UVM-Class-based-Environment
Create a task that at every clock edge initiates a forked task that computes this assertion. Read my paper Understanding the SVA Engine (link to the paper is in my signature).
module top;
import sva_delay_repeat_range_pkg::*;
int delay=2; // can be reassigned as needed later on
input_type input1, output1; // can be int, bit vector, ....
property p; // give it a meaningful name
input_type v;
(1, v=input1) ##0 dynamic_delay(delay) ##0 output1==v;
endproperty
ap_dyn_delay: assert property(@(posedge clk) p);