In reply to dave_59:
In reply to rupeshblr:
Now what you are doing makes more more sense. You are trying to write code that outputs assembly language text that will be compiled in a later step. What you have shown is informal syntax.
You need to understand the format of the assembly code from the the perspective of the compiler and express it in formal BNF production terms. Only then you can begin to use randsequence to generate random sequences of instructions based on the BNF rules. The LRM has a very simple example of this
randsequence( main )
main : first second gen ;
first : add | dec ;
second : pop | push ;
add : gen("add") ;
dec : gen("dec") ;
pop : gen("pop") ;
push : gen("push") ;
gen( string s = "done" ) : { $display( s ); } ;
endsequence
You can add random repetition and registers to this with
randsequence( main )
main : statements;
statements: repeat ($urandom_range(100,1) statement;
statement: first second gen ;
first : add | dec ;
second : pop | push ;
add : gen("add") sReg dReg endline;
dec : gen("dec") dReg endline;
pop : gen("pop\n") ;
push : gen("push\n") ;
sReg : gen($sformatf("[s%0d]",$urandom_range(127,1))) ;
dReg : gen($sformatf("[d%0d]",$urandom_range(16,1))) ;
endline : gen("\n");
gen( string s = "done" ) : { $write( s ); } ;
endsequence
Thanks Dave .
i am implementing above scenario in the below manner.
Is it not the right approach.
- created the base class.
typedef enum bit [4:0] {ADD=’h00, SUB, MUL, DIV, …} compute_path_pipe ;
typedef enum bit [3:0] { IF=’h20, ELSE, ENDIF, …} flow_control_pipe;
typedef enum bit [1:0] {MOVI=’h40, …} move_pipe;
…like i classified all the instruction
typedef enum bit [1:0] {vec1_64,…} instruction_length ;
//TYPE FORMAT
typedef enum bit[3:0] [u8,u16,…] format;
//TYPE OF REGISTER
typedef enum {sR, mR} RegType;
// 1D and 2D
typedef enum [one_D, two_D] dimesion ;
//dstmod
typedef enum {nml, sat} dstmod
//variable for declare for DDL (0 to 63)
rand logic[63:0] DDL ;
// variable for src0mod (nml | neg | abs | nabs},)
typedef enum bit[1:0] {nml, neg,…} src0mod;
//variable for emd (0,1)
rand logic emd ;
// variable for bd
rand logic bd;
class operand; (BAse class definition )
rand format format_t;
rand RegType RegType_t;
rand int Regnum;
rand int x,y,dispX,dispY,p;
rand int w,z ;
rand compute_path_pipe compute_path_pipe_t;
rand flow_control_pipe flow_control_pipe_t;
…
........
rand dimesion dimesion_t;
rand src0mod src0mod_t ;
rand dstmod dstmod_t;
constraint operand_constraint {
// x inside {[0:31]}; y inside {[0:31]}; dispX inside {[0:31]}; dispY inside {[0:31]};
// knobs is a packagege
format dist {u8:=knobs::W1,s8:= knobs::W1,u16 := knobs::W1,u32:= knobs::W1,s16:= knobs::W1,s32:= knobs::W1,f32:= knobs::W1,u64:= knobs::W1,f64 := knobs::W1};
// write constraint for regnumber wrt mR and sR
constraint regnumber_range_c {
solve Regtype before Regnum;
(Regtype_t == sR) -> Regnum inside {[0:31]};
(Regtype_t == mR) -> Regnum inside {[0:127]};
}
constraint xandy_c {
if (dimesion_t == one_D)
x inside {[0:63]};
Y
= 0;
else if (dimesion_t == two_D)
x inside {[0:7]};
y inside {[0:7]};
}
endclass
now i am creating the child component based the instruction (who has similar instruction field grouped all gather )
Example :-
class add_type extends operand ;
…
…
endclass
so like that creating the multiple child class based the instruction.
After that from top level, will create the object of child class and will randomize and will display based on Instruction mnemonics.
add_type C1;
initial begin
c1=new;
repeat(1) begin
c1.randomize();
…
$display(“c1.format=%d c1.Regtype=%d, c1.Regnum=%d, c1.x=%d,
c1.y=%d\n” ,c1.format,c1.Regtype,c1.Regnum,c1.x,c1.y);
end
end
So is this approach is correct way to achieve that.
Kindly suggest me.
Looking forward to your reply :)