In reply to rupeshblr:
I am trying to write the Constraint randomize based test to verify the the ISS (Instruction simulator ) for my processor.
Since its ISS can take assembly instruction in input but Assembly language does not provide the randomization so i used system verilog language/
how to write the constraint to replicate the below instruction.
--> IF.<condition> A <LABEL1>
..<next instruction>
......
ENDIF
LABEL1 :
Example :- IF.nz A LABEL1 ( nz – non zero)
where IF is opcode, and if condition is met with A then it will go to next instruction and end with ENDIF else go to offset (LABEL1)
typedef enum bit [3:0] { IF=’h20, ELSE, ENDIF, ENDLOOP, .......... } flow_control_pipe_t;
class operand;
rand RegType RegType_t;
rand int Regnum;
rand flow_control_pipe flow_control_pipe_t;
Constraint abc_c {
if (flow_control_pipe_t == IF )
if (A == 0) --> condition met
?????
else
???? condition not met
Kindly suggest me the how to write the code for above scenario ?
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In such cases, it is less randomization and more of proper sequencing.
Use SV’s randsequences for such a problem.
There are many articles and here is one of them: