Constraint random generation for ISS

SystemVerilog
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9

In reply to rupeshblr:

Now what you are doing makes more more sense. You are trying to write code that outputs assembly language text that will be compiled in a later step. What you have shown is informal syntax.

You need to understand the format of the assembly code from the the perspective of the compiler and express it in formal BNF production terms. Only then you can begin to use randsequence to generate random sequences of instructions based on the BNF rules. The LRM has a very simple example of this

randsequence( main )
  main : first second gen ;
  first : add | dec ;
  second : pop | push ;
  add : gen("add") ;
  dec : gen("dec") ;
  pop : gen("pop") ;
  push : gen("push") ;
  gen( string s = "done" ) : { $display( s ); } ;
endsequence

You can add random repetition and registers to this with

randsequence( main )
main : statements;
statements: repeat ($urandom_range(100,1) statement;
statement: first second gen ;
first : add | dec ;
second : pop | push ;
add : gen("add") sReg dReg endline;
dec : gen("dec") dReg endline;
pop : gen("pop\n") ;
push : gen("push\n") ;
sReg  : gen($sformatf("[s%0d]",$urandom_range(127,1))) ;
dReg  : gen($sformatf("[d%0d]",$urandom_range(16,1))) ;
endline : gen("\n"); 
gen( string s = "done" ) : { $write( s ); } ;
endsequence