In reply to shatrish:
[quote]In reply to rupeshblr:
Thank you :)
let me explain in other way ,
Specification :- i am writtting the sv based random test for ISS.
System verilog based random test (Input) and use the $display function to make assembly instruction format(.asm) --------> <<>> ------> generate the binaray code(.bin) ----> <<<<> final output(TXT File)
So i am trying to write the “System verilog based random test (Input) and use the $display function to make assembly instruction format(.asm)”
To get the above, i am writing the System verilog code constrained code and Output (basically the $display to make assembly kind program) will be Assembly code format
Lets say i want to verify the “ADD ” instruction. here my input (src0 and src1) are image input so it will have many other field which need to be constrained and randomized (thats why i choosed the SV)
Example :-ADD_.v1 <{options}>
output Should be** :-
ADD_s16.v1 mR4 [[0,0],[8,8],1] mR0 [[0,0],[8,8],2] 0 {dstmod.nml,dstszm…}
Where below field has to be randomized
format : { u8 | u16 | u32 | u64 …}
dst : …]
src0 : [[0,0],[dispX,dispY],1]
src1 : [[x,y],[dispX,dispY],1] : For sR, mR
RegType : { sR | mR }
RegNum0 to RegNum2 : { For mR, 0 to 127 | For sR, 0 to 31 }
immediate : { 0 to FFFFh }
x : { For 1D, 0 to 63 | For 2D, 0 to 7 }
y : { For 1D, always 0 | For 2D, 0 to 7 }
So like ADD, i have 200 instruction set which need to be tested.
Another example is “IF.nz A36 LABEL1”
Since i can not generate all the instruction field by writing direct test thus i am using the randomization function.