I am trying to connect one Master VIP to one Slave VIP. Now the communication between them is only through two interfaces (though they have common signals of same protocol). How to connect them in the top test bench?
I tried bind and all the trials gave error. We can’t have just the instance with common wires because the signals are not ports for the interfaces. The assign statement is the only solution?
Any standard solution exists? many of engineers say they verified VIP-VIP configuration. Please help.
The assign statement was the only one solution, finally I have landed in, which worked well. But I don’t understand why “bind” have to be restricted to only modules. Since logic/wire do not specify the direction, just tying them either through instance or “binding” shouldn’t matter, right?
Will the System Verilog committee consider the request to have the option of two interfaces binding?
The SystemVerilog bind construct is not limited to modules. You probably had some other issue related to port connections that was causing the errors. But you will need to show the code and the errors you were getting.
Even the LRM SystemVerilog 3.1a mentions only module name/instance as the target for bind. Correct me if I am wrong.
I am sure I didn’t have any errors related to port connections etc.