In reply to dave_59:
Dave,
I used as below.
bind intf1 intf2 intf12_inst (.sig11(sig21),
.sig12(sig22),
…
);
It gave the errors like below:
Can’t have interface instance as bind destination
intf1 is not a bind target
Even the LRM SystemVerilog 3.1a mentions only module name/instance as the target for bind. Correct me if I am wrong.
I am sure I didn’t have any errors related to port connections etc.