In reply to dave_59:
Thanks Dave!
The assign statement was the only one solution, finally I have landed in, which worked well. But I don’t understand why “bind” have to be restricted to only modules. Since logic/wire do not specify the direction, just tying them either through instance or “binding” shouldn’t matter, right?
Will the System Verilog committee consider the request to have the option of two interfaces binding?
Murali