Basically, the clock will be gated after 27 clock cycles cmd_debug=='h535245. I tried to run the code but the assertion fail even though the clock delta is more than 60000. Can someone point out where did I go wrong with my code, please.
In reply to lisa.lalice:
Your question is ambiguous, but let me explain what your code actually says.
@(negedge clk) // At this event
if ((clk_dis ==1) && (cmd_debug == 'h535245)) // if that is true then
##27 // I wait for 27 @(negedge clk) clocking events
@(negedge clk) (1, start=$realtime) // and then at the same @(negedge clk) clocking event
// I save the current time
|-> @(posedge clk) $realtime-start>= 60000; // and at the next poaedge clk,
// now - what I measured at the preceding negedge >= 60000;
// You may want this instead
property srf_clk_en_check_p;
realtime start;
@(negedge clk)
if ((clk_dis ==1) && (cmd_debug == 'h535245)) (1, start=$realtime)
##27 @(negedge clk) |-> @(posedge clk) $realtime-start>= 60000;
// Question: Is clock gated off here?
endproperty
// or
property srf_clk_en_check_p;
realtime start;
@(negedge clk)
(clk_dis==1 && cmd_debug==h535245, start=$realtime) ##27 1'b1 // do you have clocks?
// Are they gated here? If gated off then you do not need the ##27 ??
|-> @(posedge clk) $realtime-start>= 60000;
endproperty
// Clarify the requirements
In reply to lisa.lalice:
It looks to me that the following should work. Here you check that the next posedge clk becomes reactivated (or gated ON) sometime after 60,000ns. There is no need to use the negedge of clk if all the signals are created using the nonblocking assignment operator ( <= ) in an always block.
let SRE=24'h535245;
property srf_clk_en_check_p;
realtime start;
@(posedge clk)
(clk_enble==1 && cmd_debug==SRE, start=$realtime) ##27 1'b1 // no clocks after that
// at the next clocking event
|=> $realtime-start>= 60000ns;
endproperty
