Clock period assertion check

SystemVerilog
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4

In reply to lisa.lalice:
It looks to me that the following should work. Here you check that the next posedge clk becomes reactivated (or gated ON) sometime after 60,000ns. There is no need to use the negedge of clk if all the signals are created using the nonblocking assignment operator ( <= ) in an always block.


let SRE=24'h535245;
property srf_clk_en_check_p;
    realtime start;
    @(posedge clk)
    (clk_enble==1 && cmd_debug==SRE, start=$realtime) ##27 1'b1 // no clocks after that 
         // at the next clocking event  
               |=>  $realtime-start>= 60000ns;
  endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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