Clock period assertion check

SystemVerilog
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2

In reply to lisa.lalice:
Your question is ambiguous, but let me explain what your code actually says.


@(negedge clk) // At this event 
if ((clk_dis ==1) && (cmd_debug == 'h535245)) // if that is true then 
    ##27 // I wait for 27 @(negedge clk) clocking events 
@(negedge clk) (1, start=$realtime) // and then at the same @(negedge clk) clocking event  
               // I save the current time 
 |-> @(posedge clk) $realtime-start>= 60000;  // and at the next poaedge clk, 
    // now - what I measured at the preceding negedge >= 60000; 

// You may want this instead
property srf_clk_en_check_p;
  realtime start;
  @(negedge clk)
  if ((clk_dis ==1) && (cmd_debug == 'h535245)) (1, start=$realtime)
    ##27 @(negedge clk)  |-> @(posedge clk) $realtime-start>= 60000;
// Question: Is clock gated off here? 
endproperty

// or 
property srf_clk_en_check_p;
  realtime start;
  @(negedge clk)
  (clk_dis==1 && cmd_debug==h535245, start=$realtime) ##27 1'b1 // do you have clocks? 
       // Are they gated here?  If gated off then you do not need the ##27 ?? 
             |-> @(posedge clk) $realtime-start>= 60000;
endproperty
// Clarify the requirements

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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