Check problem

SystemVerilog
1

Hi All,
If i use function to be the sequence expr, is it legal?
like this
@rose(a) → B(x,y) ##1 c, where B is a function or task. a,c are signal.
I want to check signal c after B returns 1
Thank you

2

In reply to peter:
There are some caveats in using functions as an expression:

  • If the function has a return then you can use it
function int B(bit m, n); return m && n; endfunction
ap_p1: assert property(@(posedge clk) $rose(a) |-> B(x,y) ##1 c); // OK
ap_p2: assert property(@(posedge clk) $rose(a) |-> d==B(x,y) ##1 c); // OK
  • Function with return type of void cannot be used in/as an expression.
  • tasks cannot be used as an expression.
  • Void functions and tasks can be used in a sequence_match_item
  • You should avoid using tasks in an assertion, particularly if the task is time consuming

    function void inc_sop(bit c);
        sop_count=sop_count+1;
    endfunction: inc_sop
    
    // ERROR:  Function with return type of void cannot be used in/as an expression.
    ap_ERROR: assert property(1 |-> inc_sop(sop));

    // OK 
    ap_OK: assert property(1 |-> (1, inc_sop(sop)) );

    task automatic inc2_sop(bit c);
        sop_count=sop_count+1;
    endtask: inc2_sop
    
    ap_OK2: assert property(w |-> (e,inc_sop(sop)));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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3

In reply to ben@SystemVerilog.us:

Hi Ben, you mentioned that avoid using tasks in an assertion, particularly if the task is time consuming.What is the reason?

I have a task A() .Signal x will be driven in A(). When X is driven to be one, signal c should be 1 too.
assert property(@(posedge clk) rose(a) |-> (1,A()) ##[1:] ($rose(x)&c));

Is it ok to do that?
Thank you

4

In reply to peter:

In reply to ben@SystemVerilog.us:
Hi Ben, you mentioned that avoid using tasks in an assertion, particularly if the task is time consuming.What is the reason?

I have a task A() .Signal x will be driven in A(). When X is driven to be one, signal c should be 1 too.
assert property(@(posedge clk) rose(a) |-> (1,A()) ##[1:] ($rose(x)&c));
Is it ok to do that?

NOT recommneded. Here


task automatic A(); 
   ...
   x<=a_value; 
endtask
assert property(@(posedge clk) $rose(a) |-> (1,A()) ##[1:$] ($rose(x)&c));
  • The assertion is used as a generator and a driver.
  • An assertion should be used to verify the properties of the design, and not as a generator.
  • Errors may be created. Example:
    At t10 a rose(a) causes A() to change x at t40. // thread1
    At t20 a rose(a) causes A() to change x at t30. // thread2
    Thread1 does not see the x intended to change at t40 because thread2 made x change at t30.

Again, mixing test vector generation inside the verification model is not a good practice.
It’s hog-wash.