Can we use always block inside `ifdef?

SystemVerilog
,
3

In reply to Abhijitsjadhav:

One of the way to change the value of data depending on a signal can be as follows :


module test(input logic sel);
  `ifdef A1
      `define data(xx) (xx+2)
  `elsif A2
      `define data(xx) (sel)? (xx+2) : (xx+3)
  `else
      `define data(xx) (xx+2)
  `endif
endmodule