Can we use always block inside `ifdef?

SystemVerilog
,
1

Please look at below code
I have three different models A1,A2 and A3, where I want to give different mapping. So I am using `ifdef compiler directive.
But for A2 model I want to use seperate mapping depending on sel bit.
So can I use always block inside ifdef to write this code as below?

module test(input logic sel);
`ifdef A1
`define data(xx) (xx+2)
`elsif A2
always@(*)
begin
if(sel ==1)
`define data(xx) (xx+2)
else
`define data(xx) (xx+3) 
end
`else
`define data(xx) (XX+3)
endif
endmodule

Is there any other methods to write this logic?

2

In reply to Abhijitsjadhav:

As per the question, you can have always @* inside ifdefs for different functionality, but you cannot define macros based on signal values. This means you can have the following:


`ifdef A1
always @*
//... logic 1
`elsif A2
always @*
//... logic 2
`endif

Since macros are unrolled at compile time, you cannot define macros depending on some sel value. You can have something like follows:

`ifdef A1
`define data(xx) (xx+2)
always @* 
//...
`elsif A2
`define data(xx) (xx+3) 
always @* 
//...
`else
`define data(xx) (XX+4)
always @* 
//...
`endif
endmodule
3

In reply to Abhijitsjadhav:

One of the way to change the value of data depending on a signal can be as follows :


module test(input logic sel);
  `ifdef A1
      `define data(xx) (xx+2)
  `elsif A2
      `define data(xx) (sel)? (xx+2) : (xx+3)
  `else
      `define data(xx) (xx+2)
  `endif
endmodule
4

In reply to sharat:

Thanks you @sharvil111, @sharat for your quick response.

@sharat, But as per @sharvil11 response we cannot define macros based on signal values,and here `define is based on “sel” signal.

5

In reply to Abhijitsjadhav:

We cannot define macros as per signal values, but the behavior of macros can be altered as per signal. Lets look at following example:

`ifdef A1
`define my(sig) $display("A1 sig = %0p",sig);
`elsif A2
`define my(sig) $display("***A2 sig = %0p ***",sig);
`else 
`define my(sig) $display("### Def sig = %0p ###",sig);
`endif
always @* begin
//... 
sel = 1'b1; // some_other_signal
`my(sel)
end

// Output:
// Using +define+A1 : A1 sig = 1
// Using +define+A2 : ***A2 sig = 1 ***
// Default : ### Def sig = 1 ###

We can alter the behavior of macro, depending on sel, but we cannot define macro based on sel.

6

In reply to Abhijitsjadhav:

In reply to sharat:
Thanks you @sharvil111, @sharat for your quick response.
@sharat, But as per @sharvil11 response we cannot define macros based on signal values,and here `define is based on “sel” signal.

The macros cannot be defined conditionally based on a signal value as they are unrolled at compiled time as sharvil11 mentioned. In the example that I provided, the macro is not defined conditionally, the value of data is being calculated conditionally.

7

In reply to sharvil111:

In reply to Abhijitsjadhav:
We cannot define macros as per signal values, but the behavior of macros can be altered as per signal. Lets look at following example:

`ifdef A1
`define my(sig) $display("A1 sig = %0p",sig);
`elsif A2
`define my(sig) $display("***A2 sig = %0p ***",sig);
`else 
`define my(sig) $display("### Def sig = %0p ###",sig);
`endif
always @* begin
//... 
sel = 1'b1; // some_other_signal
`my(sel)
end
// Output:
// Using +define+A1 : A1 sig = 1
// Using +define+A2 : ***A2 sig = 1 ***
// Default : ### Def sig = 1 ###

We can alter the behavior of macro, depending on sel, but we cannot define macro based on sel.

@sharvil111 , how can I apply my above logic?, I am not getting any clue

8

In reply to sharat:

In reply to Abhijitsjadhav:
The macros cannot be defined conditionally based on a signal value as they are unrolled at compiled time as sharvil11 mentioned. In the example that I provided, the macro is not defined conditionally, the value of data is being calculated conditionally.

@sharat, I tried with your way, But I am getting below error,

Verilog HDL error at : can’t resolve reference to object “”

9

In reply to Abhijitsjadhav:

In reply to sharat:
@sharat, I tried with your way, But I am getting below error,
Verilog HDL error at : can’t resolve reference to object “”

Can you please post the code for which you are getting the error?

10

In reply to sharat:

@sharat, Code is too big, the behavior is same as I have posted in the question code.

In your initial solution
Actually if I pass parameter instead of input value “sel” I am not getting any error. and compilation is successful.

Also whatever code I have given in question, for that compilation is successful, but problem is only else part of that code is working .

11

In reply to Abhijitsjadhav:
No one is going to be able to help you without showing the code that is not working and explaining what you expect it to be doing versus what you observe it doing.

12

In reply to dave_59:

Yes that’s true dave_59, but code is about 800 line.
I will try to minimize the logic, and will post the code.

13

In reply to sharat:

I am using the code as follows,

module test(*);
  initial begin
    signal_1 = 0;
    signal_2 = 0;
    .....
  end
  // logic ///
  ...
`ifndef DATA
   initial begin
    signal_1 =100;
    signal_2 = 100;
   end

do these two initial blocks conflict?

14

In reply to Sanjeeva Dinesh:

If DATA is not define, you have a race condition between the two initial blocks.

It would help to ask this as a new question topic as this has little to do with the original thread question - it makes it easier to search for similar issues.