Please look at below code
I have three different models A1,A2 and A3, where I want to give different mapping. So I am using `ifdef compiler directive.
But for A2 model I want to use seperate mapping depending on sel bit.
So can I use always block inside ifdef to write this code as below?
As per the question, you can have always @* inside ifdefs for different functionality, but you cannot define macros based on signal values. This means you can have the following:
In reply to sharat:
Thanks you @sharvil111, @sharat for your quick response. @sharat, But as per @sharvil11 response we cannot define macros based on signal values,and here `define is based on “sel” signal.
The macros cannot be defined conditionally based on a signal value as they are unrolled at compiled time as sharvil11 mentioned. In the example that I provided, the macro is not defined conditionally, the value of data is being calculated conditionally.
In reply to Abhijitsjadhav:
We cannot define macros as per signal values, but the behavior of macros can be altered as per signal. Lets look at following example:
`ifdef A1
`define my(sig) $display("A1 sig = %0p",sig);
`elsif A2
`define my(sig) $display("***A2 sig = %0p ***",sig);
`else
`define my(sig) $display("### Def sig = %0p ###",sig);
`endif
always @* begin
//...
sel = 1'b1; // some_other_signal
`my(sel)
end
// Output:
// Using +define+A1 : A1 sig = 1
// Using +define+A2 : ***A2 sig = 1 ***
// Default : ### Def sig = 1 ###
We can alter the behavior of macro, depending on sel, but we cannot define macro based on sel.
@sharvil111 , how can I apply my above logic?, I am not getting any clue
In reply to Abhijitsjadhav:
The macros cannot be defined conditionally based on a signal value as they are unrolled at compiled time as sharvil11 mentioned. In the example that I provided, the macro is not defined conditionally, the value of data is being calculated conditionally.
@sharat, I tried with your way, But I am getting below error,
Verilog HDL error at : can’t resolve reference to object “”
In reply to Abhijitsjadhav:
No one is going to be able to help you without showing the code that is not working and explaining what you expect it to be doing versus what you observe it doing.
If DATA is not define, you have a race condition between the two initial blocks.
It would help to ask this as a new question topic as this has little to do with the original thread question - it makes it easier to search for similar issues.