Can we use always block inside `ifdef?

SystemVerilog
,
13

In reply to sharat:

I am using the code as follows,

module test(*);
  initial begin
    signal_1 = 0;
    signal_2 = 0;
    .....
  end
  // logic ///
  ...
`ifndef DATA
   initial begin
    signal_1 =100;
    signal_2 = 100;
   end

do these two initial blocks conflict?