In reply to sharat:
In reply to Abhijitsjadhav:
The macros cannot be defined conditionally based on a signal value as they are unrolled at compiled time as sharvil11 mentioned. In the example that I provided, the macro is not defined conditionally, the value of data is being calculated conditionally.
@sharat, I tried with your way, But I am getting below error,
Verilog HDL error at : can’t resolve reference to object “”