In reply to Beeri:
it is possible not to use full path.
Yes, use the $asserton and $assertoff without any arguments, as shown below.
Simulation produced the following results:
run 100ns
0 top_tb.my_control_1.disable_assertions_during_reset Disabling assertions during init..
55 top_tb.my_control_1.disable_assertions_during_reset Enabling assertions after init..
FAIL RTL at t- 55, a==0
FAIL RTL at t- 65, a==0
FAIL RTL at t- 75, a==0
FAIL RTL at t- 85, a==0
PASS RTL at t- 95, a==1
module my_control (input bit clk, a, b);
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
//$assertoff (0, top_tb.cpu_rtl_1);
$assertoff;
@ (top_tb.reset_n ==1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
//$asserton (0, top_tb.cpu_rtl_1);
$asserton;
end
always_comb ap_0: assert property (@(posedge clk) a) else $display("fail, my control a==%b", $sampled(a));
endmodule : my_control
module cpu_rtl(input bit clk, a, b);
ap_0rtl: assert property (@(posedge clk) a)
$display("PASS RTL at t-%t, a==%b", $time, $sampled(a));
else $display("FAIL RTL at t-%t, a==%b", $time, $sampled(a));
endmodule
module top_tb;
bit clk=1'b0, reset_n=1'b0, a=1, b=0;
initial forever #5 clk=!clk;
//bus_if b_if;
cpu_rtl cpu_rtl_1(clk, a, b); // Instantiation of cpu module
my_control my_control_1(clk, a, b); // instantiation of assertion control
always
begin
repeat(3) @(posedge clk);
a <=1'b0;
repeat(3) @(posedge clk);
reset_n<=1'b1;
repeat(3) @(posedge clk);
a <=1'b1;
repeat(3) @(posedge clk);
a <=1'b0;
end
// .. */
endmodule : top_tb