Hello.
In order to turn off an immediate assertion, I need to specify its full path.
i.e: $assertoff (test.a_sc.ASRT)
Is there a way not to specify the full path?
i.e: $assertoff (ASRT) [this method does not work].
If not, is the only way is to wrap the assertion with ‘if’ statement, when I want to disable it?
Snapshot of current code:
module test;
bit a;
always begin : a_sc
ASRT: assert (a)
else $assertoff (test.a_sc.ASRT);
end
endmodule
Thanks
Beeri
Below is an application from my SVA book; it explains the use of the #assertoff.
module my_control ();
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
$assertoff (0, top_tb.cpu_rtl_1);
@ (top_tb.reset_n === 1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
$asserton (0, top_tb.cpu_rtl_1);
end
endmodule : my_control
module top_tb;
logic clk =1’b0, reset_n = 1’b0;
bus_if b_if;
cpu_rtl cpu_rtl_1(clk, reset_n, .*); // Instantiation of cpu module
my_control my_control_1(); // instantiation of assertion control
..
endmodule : top_tb
Figure 4.1.4.1.5 Application of the $asserton / $assertoff in a Testbench
Ben Cohen http://www.systemverilog.us/
In reply to ben@SystemVerilog.us:
Ben,
Thank you, but you are using full hierarchy path in your example.
My question was if it is possible not to use full path.
Any idea?
Thanks
Beeri
In reply to Beeri:
it is possible not to use full path.
Yes, use the $asserton and $assertoff without any arguments, as shown below.
Simulation produced the following results:
run 100ns
module my_control (input bit clk, a, b);
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
//$assertoff (0, top_tb.cpu_rtl_1);
$assertoff;
@ (top_tb.reset_n ==1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
//$asserton (0, top_tb.cpu_rtl_1);
$asserton;
end
always_comb ap_0: assert property (@(posedge clk) a) else $display("fail, my control a==%b", $sampled(a));
endmodule : my_control
module cpu_rtl(input bit clk, a, b);
ap_0rtl: assert property (@(posedge clk) a)
$display("PASS RTL at t-%t, a==%b", $time, $sampled(a));
else $display("FAIL RTL at t-%t, a==%b", $time, $sampled(a));
endmodule
module top_tb;
bit clk=1'b0, reset_n=1'b0, a=1, b=0;
initial forever #5 clk=!clk;
//bus_if b_if;
cpu_rtl cpu_rtl_1(clk, a, b); // Instantiation of cpu module
my_control my_control_1(clk, a, b); // instantiation of assertion control
always
begin
repeat(3) @(posedge clk);
a <=1'b0;
repeat(3) @(posedge clk);
reset_n<=1'b1;
repeat(3) @(posedge clk);
a <=1'b1;
repeat(3) @(posedge clk);
a <=1'b0;
end
// .. */
endmodule : top_tb
In reply to ben@SystemVerilog.us:
You can also use the
$assertcontrol(OFF);
$assertcontrol(ON);
This is 1800’2012, and some tools support it.
module my_control (input bit clk, a, b);
// Assertion controls
let LOCK = 1; // assertion control type
let UNLOCK = 2; // assertion control type
let ON = 3; // assertion control type
let OFF = 4; // assertion control type
let KILL = 5; // assertion control type
let PASSON = 6; // assertion control type
let PASSOFF = 7; // assertion control type
let FAILON = 8; // assertion control type
let FAILOFF = 9; // assertion control type
let NONVACUOUSON = 10; // assertion control type
let VACUOUSOFF = 11; // assertion control type
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
//$assertoff (0, top_tb.cpu_rtl_1);
// $assertoff;
$assertcontrol(OFF); // using default values of all other arguments
@ (top_tb.reset_n ==1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
//$asserton (0, top_tb.cpu_rtl_1);
//$asserton;
$assertcontrol(ON);
end
always_comb ap_0: assert property (@(posedge clk) a) else $display("fail, my control a==%b", $sampled(a));
endmodule : my_control
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Thank you Ben,
I’ll try to be more specific:
Please consider the following example:
I am trying to disable ‘CHK_ASRT’ only, not ‘CHK_ASRT2’.
Here it disable both.
Any solution without full path?
Thanks
Beeri
module test ();
shortint unsigned err_cnt;
initial begin : bg
fork
repeat (10) begin
CHK_ASRT:
assert ('0)
else begin
err_cnt++;
$error ("Found error #1");
//I only want to disable this checker
if (err_cnt == 2) $assertoff ; //But this also disables 'CHK_ASRT2'.
end
#1;
end
repeat (10) begin
CHK_ASRT_2:
assert ('0)
else
$error ("Found error #2");
//This checker should not be disabled, but the '$assertoff' disabled also this one
#1;
end
join
$finish;
end
endmodule : test
In reply to Beeri:
You could use an “if” statement as shown below.
module test ();
shortint unsigned err_cnt;
bit a_en;
initial begin : bg
a_en=1'b1;
fork
repeat (10) begin
if(a_en) CHK_ASRT: assert ('0)
else begin
err_cnt++;
$error ("Found error #1");
//I only want to disable this checker
if (err_cnt == 2) a_en=1'b0; // $assertoff ; //But this also disables 'CHK_ASRT2'.
end
#1;
end
repeat (10) begin
CHK_ASRT_2:
assert ('0)
else
$error ("Found error #2");
//This checker should not be disabled, but the '$assertoff' disabled also this one
#1;
end
join
$finish;
end
endmodule : test