In reply to ben@SystemVerilog.us:
You can also use the
$assertcontrol(OFF);
$assertcontrol(ON);
This is 1800’2012, and some tools support it.
module my_control (input bit clk, a, b);
// Assertion controls
let LOCK = 1; // assertion control type
let UNLOCK = 2; // assertion control type
let ON = 3; // assertion control type
let OFF = 4; // assertion control type
let KILL = 5; // assertion control type
let PASSON = 6; // assertion control type
let PASSOFF = 7; // assertion control type
let FAILON = 8; // assertion control type
let FAILOFF = 9; // assertion control type
let NONVACUOUSON = 10; // assertion control type
let VACUOUSOFF = 11; // assertion control type
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
//$assertoff (0, top_tb.cpu_rtl_1);
// $assertoff;
$assertcontrol(OFF); // using default values of all other arguments
@ (top_tb.reset_n ==1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
//$asserton (0, top_tb.cpu_rtl_1);
//$asserton;
$assertcontrol(ON);
end
always_comb ap_0: assert property (@(posedge clk) a) else $display("fail, my control a==%b", $sampled(a));
endmodule : my_control
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115