Below is an application from my SVA book; it explains the use of the #assertoff.
module my_control ();
initial begin : disable_assertions_during_reset
$display ("%0t %m Disabling assertions during init..", $time);
$assertoff (0, top_tb.cpu_rtl_1);
@ (top_tb.reset_n === 1'b1);
$display ("%0t %m Enabling assertions after init..", $time);
$asserton (0, top_tb.cpu_rtl_1);
end
endmodule : my_control
module top_tb;
logic clk =1’b0, reset_n = 1’b0;
bus_if b_if;
cpu_rtl cpu_rtl_1(clk, reset_n, .*); // Instantiation of cpu module
my_control my_control_1(); // instantiation of assertion control
..
endmodule : top_tb
Figure 4.1.4.1.5 Application of the $asserton / $assertoff in a Testbench
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books