In reply to ben@SystemVerilog.us:
Ben,
Thank you, but you are using full hierarchy path in your example.
My question was if it is possible not to use full path.
Any idea?
Thanks
Beeri
In reply to ben@SystemVerilog.us:
Ben,
Thank you, but you are using full hierarchy path in your example.
My question was if it is possible not to use full path.
Any idea?
Thanks
Beeri