I have the following code:
parameter W_USER_SIGNAL = X; // Where X is a number but is applied based on the configuration being used
bit [W_USER_SIGNAL-1:0] my_user_signal;
I would like the above code to handle the case where a configuration is dictating that this signal's width = 0 (signal does not actually exist). I would like to have this variable referenced at different places and the code will not break if the signal's width is 0. Is there a way to do this in System Verilog?
What I have to resort to now is to write some perl around this above code which will be pre-processed to remove this signal from the resultant pure SystemVerilog code. However, this is not a scalable solution if the above variable is referenced many times in different components of the testbench.