Zero bit width array?

SystemVerilog
,
1

I have the following code:

parameter W_USER_SIGNAL = X; // Where X is a number but is applied based on the configuration being used

bit [W_USER_SIGNAL-1:0] my_user_signal;

I would like the above code to handle the case where a configuration is dictating that this signal’s width = 0 (signal does not actually exist). I would like to have this variable referenced at different places and the code will not break if the signal’s width is 0. Is there a way to do this in System Verilog?

What I have to resort to now is to write some perl around this above code which will be pre-processed to remove this signal from the resultant pure SystemVerilog code. However, this is not a scalable solution if the above variable is referenced many times in different components of the testbench.

Thanks

2

In reply to chiragg:

You cannot declare a signal with 0 width, nor can you have an expression with 0 width. However, you can have a concatanation where some of the operands have 0 width as long as the result has non-zero width.

assign out = { {W_USER_SIGNAL==0{32'bz}}, {W_USER_SIGNAL!=0{my_user_signal}} };
3

In reply to dave_59:

Thanks for your response. It would be nice to consider adding support for what I suggest in an upcoming version of SystemVerilog. I am sure this issue affects others as well and we have to resort to heavy and ugly techniques to work around them.

4

In reply to chiragg:

Would welcome any suggestions on

  1. How to declare a zero width signal? Realize that the following is already acceptable
bit [-8:+8] axis;
  1. What value does 0-width expression have? is it 0 or unknown(x)?
5

In reply to dave_59:

  1. My suggestion is to remove support for bit [-Number:0] (is this used anywhere by anyone?) and then define bit [-1:0] as a 0 bit signal. I would like to use the following to define my signal width, and the below should work no matter what non-negative number value is in parameter W_USER_SIGNAL.

bit [W_USER_SIGNAL-1:0] my_user_signal;

  1. Just like a synthesis tool optimizes out signals, the simulator should just optimize it out and an expression in which this signal is used should just act as if the signal does not exist.
6

In reply to chiragg:

Can’t remove support for existing Verilog features, especially when all simulators already support it, and this was in the original Verilog 1.0 specification. I can assure you people use it.

Synthesis tools optimize away signals when all of their possible values has no effect on results. A signal always needs a value.

7

In reply to dave_59:

Yeah, our code is littered with code like:

`define NON_NEG_MSB( a ) ( ( a ) ? ( ( a ) - 1 ) : ( 0 ) )
parameter FOO = 8;
input wire [ `NON_NEG_MSB( FOO ) : 0 ] bar_i

Here, a value of FOO = 0 is a legal degenerate case. But there’s no way to declare a zero-width port. I’d love a better solution rather than this macro trick to represent “0” of something in verilog, but don’t have any real suggestions.

In my mind the degenerate case for a variable-width signal of zero length is an event. However that doesn’t really help much with respect to how one could implement it in the current verilog grammar.

No language is perfect…

Regards,

Mark

8

In reply to Mark Curry:

Dave, Understood. Re-answering your questions:

  1. We could come up with new syntax and I can use a macro (similar to what Mark suggests) to take care of this.

  2. It could have a value of 0.

9

In reply to chiragg:

How about this as a suggestion for language improvement. Allow declarations like so:

parameter FOO = 8;
input wire [ 0 +: FOO ] bar_i

Here I’ve taken the +: bit-select operation added in Verilog 2001, and allowed it to be used in a declaration as well (that’s new, so no backward-compatibility issues). Allow the right side range argument to be zero. If it’s zero, then the declared variable is treated EXACTLY like an event.

Synthesis would, as normal, ignore event variables.

Regards,

Mark