Zero bit width array?

SystemVerilog
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5

In reply to dave_59:

  1. My suggestion is to remove support for bit [-Number:0] (is this used anywhere by anyone?) and then define bit [-1:0] as a 0 bit signal. I would like to use the following to define my signal width, and the below should work no matter what non-negative number value is in parameter W_USER_SIGNAL.

bit [W_USER_SIGNAL-1:0] my_user_signal;

  1. Just like a synthesis tool optimizes out signals, the simulator should just optimize it out and an expression in which this signal is used should just act as if the signal does not exist.